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Design and Verification Engineer

The Programme

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Responsibilities

  • Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
  • Develop infrastructure and environment for IP/SoC level design verification.
  • Closely working with Design/Architecture/Verification team to develop new verification component.

Required Skills and Abilities

  • Major in Electrical Engineering, Computer Science or related
  • Good understanding on ASIC design verification flow
  • Good design verification experience
  • Programming knowledge on Verilog/SystemVerilog, C/C++
  • Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
  • Should have good communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
  • Strong problem solving skills
  • Job type:Graduate jobs
  • Disciplines:

    Computer Science, Engineering

  • Citizenships:

  • Locations:

    Shanghai (China)

  • Closing Date:31st Jan 2019, 6:00 pm

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