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Design Verification Intern

The Programme

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Responsibilities

  • Develop micro-architecture specification for GPU blocks.
  • Develop RTL code for GPU blocks in Verilog HDL.
  • Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
  • Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.

Required Skills and Abilities

  • Master or above degree.
  • Major in Micro-E or related, Electronic Engineer, Computer Science, Mathematics. Communication.
  • Familiar with Verilog HDL coding and ASIC Frond-End implementation flow.
  • Familiar with unix/linux and scripts (tcl, perl, python etc.).
  • Strong task-based organization skills.
  • Computer architecture and computer arithmetic (a plus).
  • Computer graphic basic knowledge (a plus).
  • Experience with Database technologies and database-driven custom web application development (a plus).
  • Proficient English and Mandarin (listening, writing and speaking).
  • Have project experience during university education.
  • Strong passion in achievement and career development.
  • A self-motivated team player
Closing in 13 days
Closing in 13 days
  • Job type:Internships
  • Disciplines:

    Communications, Computer Science, Engineering, Mathematics

  • Citizenships:

  • Locations:

    Shanghai (China)

  • Closing Date:31st Jan 2019, 6:00 pm

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