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Physical Design Intern

The Programme

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


  • Work in physical design team for large scale ASIC chip physical implementation.
  • Focus on physical design of deep sub-micron SOC chips for block level floor planning, timing closure, place&route, physical verification etc.
  • The individual is expected to be accountable for block level project delivery

Required Skills and Abilities

  • Familiar with ASIC backend design flow/methodology.
  • Knowledgeable in deep submicron ASIC design.
  • Strong problem solving skills, and attention to details
  • Good interpersonal skills (verbal and written)
  • Dedicated, hardworking and good team player
  • Familiar with Unix/Linux environment and good at scripts
  • Familiar with Back-End (physical design) EDA tools is a plus.
  • Bachelor of EE or CS. 4-5 days working per week.
  • Job type:Internships
  • Disciplines:

    Computer Science, Engineering

  • Citizenships:

  • Locations:

    Shanghai (China)

  • Closing Date:31st Jan 2019, 6:00 pm


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